As the demands of technology have increased, both the density and the multiplicity of functions performed by a given integrated circuit have increased. In addition, the speed at which data is processed through these integrated circuits has also increased. These devices are generally referred to as a large scale integrated circuits (VLSI). To reliably realize VLSI devices, new techniques have been developed to both fabricate the device at the semiconductor chip level and also to package the chip. There are some inherent disadvantages to this increased density and speed since the VLSI devices must still be interfaced with peripheral circuits and thus must have some output ports, control port, etc. Due to the large number of functions that are performed by a given VLSI chip, the number of interface connections or IC pins is relatively low as compared to the number of functions that the device performs. The result is that the internal functions are relatively inaccessible for trouble shooting and/or failure analysis, since use of interface connections must be optimized and they are generally dedicated to a functional mode of the device rather than testing modes.
Once a circuit is manufactured utilizing VSLI circuits, it is necessary to test the circuits prior to packaging thereof. This test normally consists of probing the device at the input and output pads and various test points thereon. Failures can then be determined and only acceptable devices packaged. However, in certain circuits, redundant circuit elements are provided that can be inserted in place of faulty elements. One type of circuit that this is utilized in is a semiconductor memory array wherein a redundant column is provided. When one column is determined to be defective, it is deactivated and the redundant column activated to provide a replacement therefor. This activation and deactivation is normally effected by opening polysilicon fuses that are fabricated on the integrated circuit. To open these fuses, a special test facility is provided which has a laser mounted adjacent the probing mechanism. This allows for both replacement of the defective device with the redundant circuit and also retesting thereof.
In testing integrated circuits prior to packaging thereof, speed is one important factor to be considered. Since yields can be as low as 10%, a large amount of time is utilized to test the 90% of defective devices, make a decision and reject these devices. It is therefore desirable to minimize the amount of time to perform a given test.
In addition to reducing the testing time, it is also desirable to measure the parameters of individual devices on a circuit. For a device such as a memory array where there are a large number of similar elements such as the memory cells, such factors as leakage, storage time, etc. are of paramount importance. However, the interconnections between the individual elements and interaction thereof inhibits access to the input and the output of these elements. For example, the storage capacitor in a Dynamic Random Access Memory (DRAM) is normally connected between a reference voltage and one side of a transistor. The parameters of this capacitor can only be measured by charging the capacitor through control of the transistor, with this control being the only variable. This control signal is derived from the output of either the column or row decoder and can only be tested within the constraints of the operation of the decoders. Heretofore, no provision has been made for testing the parameters of individual elements in an integrated circuit.
In view of the above disadvantages with testing the various parameters of integrated circuits, there exists a need for improved methods of performing the test by allowing access to the individual elements in the integrated circuit and also decreasing the time required for making these tests.